1. Field of the Invention
Example embodiments of the present invention relate generally to multi-processor systems and methods thereof, and more particularly to multi-processor systems and methods of initializing said multi-processor systems.
2. Description of the Related Art
A conventional mobile device, such as a personal digital assistant (PDA), may include a plurality of processors to support multiple functions. If the mobile device is turned on, each processor within a given intellectual property (IP) block may execute a program (e.g., a “boot code”) to initialize the respective IP block. Generally, a system initializing operation may check a custom setting (e.g., a complementary metal oxide semiconductor (CMOS) check), and may load an interrupt handler and device drivers. Additionally, the system initializing operation may initialize registers and device management, and may perform a power-on-self-test (POST) for components in each IP block, as well as peripheral devices.
The boot code may typically be stored in a read only memory (ROM), an erasable programmable read-only memory (EPROM) or NOR flash memory. If the boot code is stored in the ROM or the EPROM, it may be difficult to modify or refresh the boot code (e.g., because the memory is read-only). Alternatively, if the NOR flash memory is used as a storage medium for a basic input/output system (BIOS) program or boot code, the boot code may be more easily modified or erased.
FIG. 1 is a block diagram of a conventional multi-processor system. Referring to FIG. 1, the multi-processor system may include IP blocks 10, 30 and 50 connected through a system bus 60. In an example, the IP blocks 10, 30 and 50 may be embodied as a semiconductor circuit, a module and a block, respectively, with each IP block having a given function.
Referring to FIG. 1, processors 11 and 13 may utilize NOR flash memories 15 and 35 as a storage medium (e.g., a boot memory) of a BIOS program (e.g., the boot code). The respective processors 11 and 31 in the IP blocks 10 and 30 may utilize dynamic random access memories (DRAMs) 13 and 33 as a system memory. The respective processors 11 and 31 in the IP blocks 10 and 30, DRAMs 13 and 33, and NOR flash memories 15 and 35 may be connected through local buses LB1 and LB2, respectively. Each of the IP blocks 10 and 30 may further include additional peripheral devices 17 and 37, respectively.
As described above, the NOR flash memory 15 and 35 may allow the stored program to be easily modified or refreshed. However, NOR flash memory devices may be more expensive than, for example, ROM and/or EPROM devices. Also, NOR flash memory devices may have a relatively large physical size, such that a NOR flash memory device with a capacity for storing a given amount of data may be bigger than a corresponding ROM and/or EPROM device with the same storage capacity.
As illustrated in FIG. 1, if a plurality of processors includes respective boot memories implemented with a NOR flash memory, the manufacturing cost and the size may be higher. In mobile devices, physical size and manufacturing cost may be important design criteria, such that the deployment of NOR flash memory to store boot codes may make it more difficult to cheaply manufacture a relatively small-sized and multi-functional mobile device, while deploying ROM and/or EPROM memory to store boot codes may reduce the functionality of the mobile device.